Datapath Reuse in a Multi-Standard FEC Kernel

Sharing of datapath and memories across different forward error correction (FEC) decoder implementations are important in flexible wireless communication system design. In this paper, we explore datapath reuse possibilities across some important FEC families like convolutional, turbo and low density parity check (LDPC) codes. At first, design of a reduced complexity trellis network for shuffling the updated state metrics in Viterbi and Turbo decoding kernel is presented. Our design results in complexity reduction of upto 70 % compared to trellis networks implemented in state of art multi standard FEC kernels. Furthermore, the hardware reuse potential of different existing implementation schemes for check node processing in LDPC decoding is explored over such a FEC kernel architecture. In the last part of the paper, we propose a novel parallel implementation approach (”Tree-Way”) for check node processing, which fits very well with underline FEC Kernel architecture. Implementation results are presented showing that the proposed scheme provides significant speed-up in terms of required clock cycles without significant increase in combined datapath area compared to existing approaches.